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IDT82V3288BC Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT82V3288BC
Description  WAN PLL
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT82V3288BC Datasheet(HTML) 7 Page - Integrated Device Technology

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List of Tables
7
June 22, 2006
IDT82V3288
WAN PLL
Table 49: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 156
Table 50: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 156
Table 51: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 156
Table 52: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 156
Table 53: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 158
Table 54: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 159
Table 55: Output Clock Jitter Generation .................................................................................................................................................................. 160
Table 56: Output Clock Phase Noise ......................................................................................................................................................................... 161
Table 57: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 161
Table 58: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 161
Table 59: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 161
Table 60: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 161
Table 61: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 162
Table 62: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 162
Table 63: Input/Output Clock Timing 3 ...................................................................................................................................................................... 164
Table 64: Output Clock Timing .................................................................................................................................................................................. 165


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