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IDT82V3255TFG Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT82V3255TFG Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 127 page List of Figures 8 June 19, 2006 Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11 Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12 Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 19 Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 20 Figure 5. External Fast Selection ................................................................................................................................................................................ 22 Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 29 Figure 7. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 30 Figure 8. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 38 Figure 9. 0.5 UI Early Frame Sync Input Signal Timing .............................................................................................................................................. 38 Figure 10. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 39 Figure 11. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 39 Figure 12. IDT82V3255 Power Decoupling Scheme ................................................................................................................................................... 41 Figure 13. Line Card Application ................................................................................................................................................................................. 42 Figure 14. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 43 Figure 15. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 43 Figure 16. Serial Write Timing Diagram ....................................................................................................................................................................... 44 Figure 17. JTAG Interface Timing Diagram ................................................................................................................................................................. 45 Figure 18. Recommended PECL Input Port Line Termination .................................................................................................................................. 114 Figure 19. Recommended PECL Output Port Line Termination ................................................................................................................................ 114 Figure 20. Recommended LVDS Input Port Line Termination .................................................................................................................................. 116 Figure 21. Recommended LVDS Output Port Line Termination ................................................................................................................................ 116 Figure 22. Output Wander Generation ...................................................................................................................................................................... 120 Figure 23. Input / Output Clock Timing ...................................................................................................................................................................... 121 List of Figures |
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