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IDT72V85L20PAGI Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72V85L20PAGI Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 12 page 8 COMMERCIALTEMPERATURERANGE IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 JULY 17, 2006 USAGE MODES: Width Expansion Word width may be increased simply by connecting the corresponding input control signals of multiple FIFOs. Status flags ( EF, FF and HF) can be detected from any one FIFO. Figure 13 demonstrates an 18-bit word width by usingthetwoFIFOscontainedintheIDT72V81/72V82/72V83/72V84/72V85s. Any word width can be attained by adding FIFOs (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72V81/72V82/72V83/72V84/72V85s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W,calledthefirstwriteedge,anditremainsonthe busuntilthe Rline is raised from low-to-high, after which the bus would go into a three-state mode after tRHZ ns. The EFlinewouldhaveapulseshowingtemporarydeassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The Rline causes the FFto be deasserted but the Wline being low causes it to be asserted again in anticipation of a new data word. On the rising edgeof W,thenewwordisloadedintheFIFO.TheWlinemustbetoggledwhen FFisnotassertedtowritenewdataintheFIFOandtoincrementthewritepointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). Figure 12. Block Diagram of One 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 FIFO Used in Single Device Mode Figure 13. Block Diagram of One 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18 FIFO Memory Used in Width Expansion Mode XIA XIB 9 9 18 9 18 HFB HFA 9 WRITE ( W) FULL FLAG ( FFA) RESET ( RS) READ ( R) EMPTY FLAG ( EFB) RETRANSMIT ( RT) DATA OUT (Q) 3966 drw 15 FIFO A FIFO B 72V81/72V82/72V83 72V84/72V85 DATA (D) IN WRITE ( W) DATA IN (D) FULL FLAG ( FF) RESET ( RS) 9 READ ( R) 9 DATA OUT (Q) EMPTY FLAG ( EF) RETRANSMIT ( RT) EXPANSION IN ( XI) ( HF) IDT 72V81 72V82 72V83 72V84 72V85 (HALF-FULL FLAG) 3966 drw 14 FIFO A or B |
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