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CY7C1350G-133BGI Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C1350G-133BGI
Description  4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1350G-133BGI Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C1350G
Document #: 38-05524 Rev. *F
Page 3 of 15
Pin Configurations (continued)
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQA
VDDQ
NC/576M
NC/1G
DQC
DQD
DQC
DQD
AA
A
A
NC/18M
VDDQ
CE2
A
VDDQ
VDDQ
VDDQ
VDDQ
NC/144M
NC
A
DQC
DQC
DQD
DQD
NC
VDD
A
NC/72M
DQPD
A
A
ADV/LD
A
CE3
NC
VDD
AA
NC
VSS
VSS
NC
DQPB
DQB
DQB
DQA
DQB
DQB
DQA
DQA
NC
NC
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MODE
CE1
VSS
OE
VSS
VDDQ
BWC
NC/9M
VSS
WE
VDDQ
VDD
VSS
VDD
VSS
CLK
NC
BWA
CEN
VSS
VDDQ
VSS
ZZ
NC/288M
A
A
A1
A0
VSS
VDD
DQPC
DQB
A
NC/36M
DQC
DQB
DQC
DQC
DQC
DQB
DQB
DQA
DQA
DQA
DQA
DQPA
DQD
DQD
DQD
DQD
BWD
119-Ball BGA Pinout
BWB
NC
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:D]
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.


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