CY7C1351G datasheet(6/14 Pages) CYPRESS | 4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture

6 page

CY7C1351G

Document #: 38-05513 Rev. *D

Page 6 of 14

Truth Table [2, 3, 4, 5, 6, 7, 8]

Operation

Address

Used

CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK

Deselect Cycle

None

L->H

Tri-State

Deselect Cycle

None

L->H

Tri-State

Deselect Cycle

None

L->H

Tri-State

Continue Deselect Cycle

None

L->H

Tri-State

READ Cycle (Begin Burst)

External

L->H Data Out (Q)

READ Cycle (Continue Burst)

L->H Data Out (Q)

NOP/DUMMY READ (Begin Burst)

External

L->H

Tri-State

DUMMY READ (Continue Burst)

L->H

Tri-State

WRITE Cycle (Begin Burst)

External

L->H

Data In (D)

WRITE Cycle (Continue Burst)

L->H

Data In (D)

NOP/WRITE ABORT (Begin Burst)

None

L->H

Tri-State

WRITE ABORT (Continue Burst)

L->H

Tri-State

IGNORE CLOCK EDGE (Stall)

Current

L->H

–

SLEEP MODE

None

Tri-State

Partial Truth Table for Read/Write [2, 3, 9]

Function

BWA

BWB

BWC

BWD

Read

Write – No bytes written

Write Byte A – (DQA and DQPA)L

Write Byte B – (DQB and DQPB)L

Write Byte C – (DQC and DQPC)L

Write Byte D – (DQD and DQPD)

HHH

Write All Bytes

Notes:

2. X = Don’t Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write

selects are asserted, see truth table for details.

3. Write is defined by BWX, and WE. See truth table for Read/Write.

4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

5. The DQs and DQP[A:D] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tri-state when

OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

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