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IDT82V2088 Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT82V2088 Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 78 page  4 INDUSTRIAL TEMPERATURE RANGES OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.8 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 31 3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 31 3.8.2 ERROR DETECTION AND COUNTING ................................................................ 31 3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 32 3.9 LINE DRIVER FAILURE MONITORING ........................................................................... 32 3.10 MCLK AND TCLK ............................................................................................................. 33 3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 33 3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 33 3.11 MICROCONTROLLER INTERFACES ............................................................................. 34 3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 34 3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 34 3.12 INTERRUPT HANDLING .................................................................................................. 35 3.13 GENERAL PURPOSE I/O ................................................................................................ 36 3.14 5V TOLERANT I/O PINS .................................................................................................. 36 3.15 RESET OPERATION ........................................................................................................ 36 3.16 POWER SUPPLY ............................................................................................................. 36 4 PROGRAMMING INFORMATION .............................................................................................. 37 4.1 REGISTER LIST AND MAP ............................................................................................. 37 4.2 REGISTER DESCRIPTION .............................................................................................. 39 4.2.1 GLOBAL REGISTERS............................................................................................ 39 4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 41 4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 41 4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 43 4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 45 4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 48 4.2.7 LINE STATUS REGISTERS ................................................................................... 51 4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 54 4.2.9 COUNTER REGISTERS ........................................................................................ 55 4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 56 5 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 57 5.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 58 5.2 JTAG DATA REGISTER ................................................................................................... 58 5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 58 5.2.2 BYPASS REGISTER (BR)...................................................................................... 58 5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 58 5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 59 6 TEST SPECIFICATIONS ............................................................................................................ 61 7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 73 7.1 SERIAL INTERFACE TIMING .......................................................................................... 73 7.2 PARALLEL INTERFACE TIMING ..................................................................................... 74 |
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