CY7C1352G_06 datasheet(9/12 Pages) CYPRESS

Part #	CY7C1352G

Description	4-Mbit (256K x 18) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

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9 / 12 page

CY7C1352G

Document #: 38-05514 Rev. *D

Page 9 of 12

Switching Waveforms

Read/Write Timing[18, 19, 20]

Notes:

18. For this waveform ZZ is tied low.

19. When CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

20. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.

WRITE

D(A1)

123

456789

CLK

t CYC

tCL

tCH

10

CE

tCEH

tCES

WE

CEN

tCENH

tCENS

BW[A:B]

ADV/LD

tAH

tAS

ADDRESS

A1

A2

A3

A4

A5

A6

A7

tDH

tDS

Data

In-Out (DQ)

tCLZ

D(A1)

D(A2)

D(A5)

Q(A4)

Q(A3)

D(A2+1)

tDOH

tCHZ

tCO

WRITE

D(A2)

BURST

WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OE

tOEV

tOELZ

tOEHZ

tDOH

DON’T CARE

UNDEFINED

Q(A6)

Q(A4+1)

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