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IDT82V2048LDAG Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT82V2048LDAG Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 48 page 4 IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END INDUSTRIAL TEMPERATURE RANGES 1 PIN DESCRIPTION Table-1 Pin Description Name Type Pin No. Description TQFP144 PBGA160 Transmit and Receive Line Interface TTIP0 TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 TRING0 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 Analog Output 45 52 57 64 117 124 129 136 46 51 58 63 118 123 130 135 N5 L5 L10 N10 B10 D10 D5 B5 P5 M5 M10 P10 A10 C10 C5 A5 TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~7 These pins are the differential line driver outputs. They will be in high impedance state if pin OE is low or the corresponding pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In host mode, each pin can be in high impedance by programming a ‘1’ to the corresponding bit in register OE(1). RTIP0 RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 RRING0 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7 Analog Input 48 55 60 67 120 127 132 139 49 54 61 66 121 126 133 138 P7 M7 M8 P8 A8 C8 C7 A7 N7 L7 L8 N8 B8 D8 D7 B7 RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~7 These pins are the differential line receiver inputs. 1. Register name is indicated by bold capital letter. For example, OE indicates Output Enable Register. |
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