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IDT79RC64T575-200DZI Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT79RC64T575-200DZI Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 28 page  2 of 28 December 14, 2001 79RC64574™ 79RC64575™ Device Overview1 IDT’s 79RC64574/575 processors serve a wide range of perfor- mance-critical embedded applications that include high-end internet- working systems, digital set-top boxes, web browsers, color printers, and graphics terminals. The RC64574/575 allow a socket compatible upgrade path for IDT’s RC4640/50 and RC64474/475 processors. This unprecedented upgrad- ability allows a 2:1 range of frequencies; 4:1 range of cache size; 15:1 range of floating-point; and 4:1 range of DSP performance in a single socket. With special emphasis on system bandwidth, floating- point and DSP operations, the RC64574/575 have been optimized for high-perfor- mance applications through the integration of high-performance compu- tational units and a high-performance memory hierarchy. The result is a low-cost CPU that is capable of more than 330 Dhrystone MIPS. Through the RC64574/64575 processors IDT offers: ◆ High-performance upgrade paths to existing embedded customers in the internetworking, office automation and visualization markets. ◆ Significant floating-point performance improvements over currently available, moderately priced MIPS CPUs. ◆ Performance improvements through the use of the MIPS-IV ISA. ◆ High-performance DSP acceleration 1. Detailed system operation information is provided in the RC64574/RC64575 user’s manual. Instruction Issue Mechanism The RC64574 and RC64575 are limited dual-issue super-scalar machines that use a traditional 5-stage integer pipeline, as shown in the pipeline diagram on Page 3. For multi-issue operations, these devices recognize the following two general classes of instructions: ◆ Floating-point ALU ◆ All others Such a broad separation of instruction classes insure that there are no data dependencies to restrict multi-issue performance. As they are brought on-chip, these instruction classes are pre-decoded by the RC64574/575, and the class information is then stored in the instruction cache. Assuming there are no pending resource conflicts, the devices can issue one instruction per class per pipeline clock cycle. However, longer latency resources—in either the floating-point ALU (for example, division or square root instructions) or integer unit (such as multiply)—can restrict the issue of instructions. Note that these proces- sors do not perform out-of-order or speculative execution; instead, the pipeline slips until the required resource becomes available. On dual-issue instruction pairs, there are no alignment restrictions, and the RC64574/575 fetch two instructions from the cache per cycle. Thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, because the instruc- tion cache only performs aligned fetches. RISCore4000/RISCore5000 Family of Socket Compatible Processors 32-bit External Bus Processors 64-bit External Bus Processors RC4640 RC64474 RC64574 RC4650 RC64475 RC64575 CPU 64-bit RISCore4000 w/ DSP extensions 64-bit RISCore4000 64-bit RISCore5000 w/ DSP extensions 64-bit RISCore4000 w/ DSP extensions 64-bit RISCore4000 64-bit RISCore5000 w/ DSP extensions Performance >350MIPS >330MIPS >330MIPS >350MIPS >330MIPS >330MIPS FPA 89 mflops, single preci- sion only 125 mflops, single and double precision 666 mflops, single and double precision 89 mflops, single preci- sion only 125 mflops, single and double precision 666 mflops, single and double precision Caches 8kB/8kB, 2-way, lockable by set 16kB/16kB, 2-way, lockable by set 32kB/32kB, 2-way, lockable by line 8kB/8kB, 2-way, lockable by set 16kB/16kB, 2-way, lockable by set 32kB/32kB, 2-way, lockable by line External Bus 32-bit 32-bit, Superset pin compatible w/RC4640 32-bit, Superset pin compatible w/RC4640, RC64474 32- or 64-bit 32-or 64-bit, Superset pin compatible w/ RC4650 32-or 64-bit, Superset pin compatible w/ RC4650, RC64475 Voltage 3.3V 3.3V 2.5V 3.3V 3.3V 2.5V Frequencies 100-267 MHz 180-250 MHz 200-250 MHz 100-267 MHz 180-250 MHz 250 MHz Packages 128 PQFP 128 QFP 128 QFP 208 QFP 208 QFP 208 QFP MMU Base-Bounds 96 page TLB 96 page TLB Base-Bounds 96 page TLB 96 page TLB Key Features Cache locking, on-chip MAC, 32-bit external bus Cache locking, JTAG, syncDRAM mode, 32-bit external bus Cache locking, JTAG, syncDRAM mode, 32-bit external bus Cache locking, on-chip MAC, 32-bit & 64 bit bus option Cache locking, JTAG, syncDRAM mode, 32- 64- bit bus option Cache locking, JTAG, syncDRAM mode, 32- 64- bit bus option Table 1 RISCore4000/RISCore5000 Processor Family |
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