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IDT79RC64T574-250DZI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT79RC64T574-250DZI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 28 page 7 of 28 December 14, 2001 79RC64574™ 79RC64575™ Pin Description Table The following is a list of system interface pins available on the RC64574/575. Pin names ending with an asterisk (*) are active when low. Pin Name Type Description System Interface ExtRqst* I External request An external agent asserts ExtRqst* to request use of the System interface. The processor grants the request by asserting Release*. Release* O Release interface In response to the assertion of ExtRqst* or a CPU read request, the processor asserts Release* and signals to the requesting device that the system interface is available. RdRdy* I Read Ready The external agent asserts RdRdy* to indicate that it can accept a processor read request. WrRdy* I Write Ready An external agent asserts WrRdy* when it can now accept a processor write request. ValidIn* I Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. ValidOut* O Valid Output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. SysAD(63:0) I/O System address/data bus A 64-bit address and data bus for communication between the processor and an external agent. In 64 bit interface mode, during address phases only, SysAd(35:0) contains invalid address information. The remain- ing SysAD(63:36) pins are not used. The whole 64-bit SysAD(63:0) may be used during the data transfer phase. For all double-word accesses (read or write), the low-order 3 bits (SysAD[2:0]) will always be output as zero during the address phase. In 32-bit interface mode and in the RC64574, SysAD(63:32) is not used, regardless of Endianness. A 32-bit address and data communication between processor and external agent is performed via SysAD(31:0). SysADC(7:0) I/O System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. In 32-bit mode and in the RC64574, SysADC(7:4) is not used. The SysADC(3:0) contains check bits for SysAD(31:0). SysCmd(8:0) I/O System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysCmdP I/O System Command Parity A single, even-parity bit for the Syscmd bus. This signal is always driven low. Clock/Control Interface SysClock I SystemClock The system clock input establishes the processor and bus operating frequency. It is multiplied internally by 2,3,4,5,6,7, or 8 to generate the pipeline clock (PClock). VCCPI Quiet VCC for PLL Quiet VCC for the internal phase locked loop. VSSPI Quiet VSS for PLL Quiet VSS for the internal phase locked loop. Table 5 Pin Descriptions (Page 1 of 2) |
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