Rev.01
16Mb SDRAM
4/18
Pin
Name
Pin Function
CLK
System Clock
Master Clock Input(Active on the Positive rising edge)
/CS
Chip select
Selects chip when active
CKE
Clock Enable
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
A0 ~ A10
Address
Row address (A0 to A10) is determined by A0 to A10 level
at the bank active command cycle CLK rising edge.
CA(CA0 to CA7) is determined by A0 to A7 level at the
read or write command cycle CLK rising edge.
And this column address becomes burst access start
address. A10 defines the pre-charge mode. When A10 = High
at the pre-charge command cycle, all banks are pre-charged.
But when A10 = Low at the pre-charge command cycle,
only the bank that is selected by BA is pre-charged.
/RAS
Row address strobe
Latches Row Addresses on the positive rising edge of the
CLK with /RAS “L”. Enables row access & pre-charge.
/CAS
Column address strobe
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
/WE
Write Enable
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
UDQM /LDQM
Data input/output Mask
DQM controls I/O buffers.
DQ0 ~ 15
Data input/output
DQ pins have the same function as I/O pins on a conventional
DRAM.
VDD/VSS
Power supply/Ground
VDD and VSS are power supply pins for internal circuits.
Pin Descriptions ( Simplified )
BA
Bank Address
Selects which bank is to be active.
NC
No connection
This pin is recommended to be left No Connection on the
device.
VDDQ/VSSQ
Power supply/Ground
VDDQ and VSSQ are power supply pins for the output buffers.
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