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IDT79RC64V474-180DPI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT79RC64V474-180DPI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 25 page 7 of 25 April 10, 2001 RC64474™ RC64475™ Pin Description Table The following is a list of system interface pins available on the RC64474/475. Pin names ending with an asterisk (*) are active when low. Pin Name Type Description System Interface ExtRqst* I External request An external agent asserts ExtRqst* to request use of the System interface. The processor grants the request by asserting Release*. Release* O Release interface In response to the assertion of ExtRqst* or a CPU read request, the processor asserts Release* and signals to the request- ing device that the system interface is available. RdRdy* I Read Ready The external agent asserts RdRdy* to indicate that it can accept a processor read request. WrRdy* I Write Ready An external agent asserts WrRdy* when it can now accept a processor write request. ValidIn* I Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data iden- tifier on the SysCmd bus. ValidOut* O Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. SysAD(63:0) I/O System address/data bus A 64-bit address and data bus for communication between the processor and an external agent. During address phases only, SysAd(35:0) contains valid address information. The remaining SysAD(63:36) pins are not used. The whole 64-bit SysAD(63:0) may be used during the data transfer phase. In 32-bit mode and in the RC64474, SysAD(63:32) is not used, regardless of Endianness. A 32-bit address and data com- munication between processor and external agent is performed via SysAD(31:0). SysADC(7:0) I/O System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. In 32-bit mode and in the RC64474, SysADC(7:4) is not used. The SysADC(3:0) contains check bits for SysAD(31:0). SysCmd(8:0) I/O System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysCmdP I/O System Command Parity A single, even-parity bit for the Syscmd bus. This signal is always driven low. Clock/Control Interface MasterClock I Master Clock Master clock input establishes the processor and bus operating frequency. It is multiplied internally by 2,3,4,5,6,7,8 to gen- erate the pipeline clock (PClock). This clock must be driven by 3.3V (Vcc) clock signals, regardless of the 5V tolerant pin setting. VCCP I Quiet VCC for PLL Quiet VCC for the internal phase locked loop. VSSPI Quiet VSS for PLL Quiet VSS for the internal phase locked loop. Interrupt Interface Int*(5:0) I Interrupt Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. Table 5 Pin Descriptions (Page 1 of 2) |
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