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IDT82V2048SDA Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT82V2048SDA Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 62 page  6 IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED INDUSTRIAL TEMPERATURE RANGES RD0/RDP0 RD1/RDP1 RD2/RDP2 RD3/RDP3 RD4/RDP4 RD5/RDP5 RD6/RDP6 RD7/RDP7 CV0/RDN0 CV1/RDN1 CV2/RDN2 CV3/RDN3 CV4/RDN4 CV5/RDN5 CV6/RDN6 CV7/RDN7 O High-Z 40 33 77 70 111 104 5 142 41 34 76 69 112 105 4 141 P2 M2 M13 P13 A13 C13 C2 A2 P3 M3 M12 P12 A12 C12 C3 A3 RDn: Receive Data for Channel 0~7 In Single Rail mode, the received NRZ data is output on this pin. The data is decoded by AMI or B8ZS/ HDB3 line code rule. CVn: Code Violation for Channel 0~7 In Single Rail mode, the bipolar violation, code violation and excessive zeros will be reported by driving pin CVn high for a full clock cycle. However, only bipolar violation is indicated when AMI decoder is selected. RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7 In Dual Rail Mode with clock recovery, these pins output the NRZ data. A high signal on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the receipt of a negative pulse on RTIPn/RRINGn. The output data at RDn or RDPn/RDNn are clocked out on the falling edges of RCLK when the CLKE input is low, or are clocked out on the rising edges of RCLK when CLKE is high. In Dual Rail Mode without clock recovery, these pins output the raw RZ sliced data. In this data recovery mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is low, RDPn/RDNn is active low. When pin CLKE is high, RDPn/RDNn is active high. In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will either remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE in regis- ter GCF. RDn or RDPn/RDNn is set into high-Z when the corresponding receiver is powered down. RCLK0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 O High-Z 39 32 78 71 110 103 6 143 P1 M1 M14 P14 A14 C14 C1 A1 RCLKn: Receive Clock for Channel 0~7 In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn. The received data are clocked out of the device on the rising edges of RCLKn if pin CLKE is high, or on falling edges of RCLKn if pin CLKE is low. In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with RDPn and RDNn. The clock is recovered from the signal on RCLKn. If Receiver n is powered down, the corresponding RCLKn is in high-Z. MCLK I 10 E1 MCLK: Master Clock This is an independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) is supplied to this pin as the clock reference of the device for normal operation. In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse (Data Recovery mode). When MCLK is low, all the receivers are powered down, and the output pins RCLKn, RDPn and RDNn are switched to high-Z. In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn pin description for details). NOTE: Wait state generation via RDY/ACK is not available if MCLK is not provided. LOS0 LOS1 LOS2 LOS3 LOS4 LOS5 LOS6 LOS7 O 42 35 75 68 113 106 3 140 K4 K3 K12 K11 E11 E12 E3 E4 LOSn: Loss of Signal Output for Channel 0~7 A high level on this pin indicates the loss of signal when there is no transition over a specified period of time or no enough ones density in the received signal. The transition will return to low automatically when there is enough transitions over a specified period of time with a certain ones density in the received sig- nal. The LOS assertion and desertion criteria are described in 2.4.5 Loss of Signal (LOS) Detection. Table-1 Pin Description (Continued) Name Type Pin No. Description TQFP144 PBGA160 |
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