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P4C1256-15TMBLF Datasheet(PDF) 8 Page - Pyramid Semiconductor Corporation |
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P4C1256-15TMBLF Datasheet(HTML) 8 Page - Pyramid Semiconductor Corporation |
8 / 17 page P4C1256 Page 8 of 17 Document # SRAM119 REV G Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 AC TEST CONDITIONS Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1256, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 Ω test environment should be terminated into a 50 Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 Ω resistor must be used in series with D OUT to match 166Ω (Thevenin Resistance). Write Active Read TRUTH TABLE Mode Standby Standby D OUT Disabled Standby Power I/O WE WE WE WE WE OE OE OE OE OE CE CE CE CE CE High Z High Z D OUT High Z X X H H L X X H L X H L L L Standby Active Active High Z X |
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