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IDT72265LA10TFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72265LA10TFG Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 27 page  1 2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4670/2 OCTOBER 2005 CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18 IDT72255LA IDT72265LA IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SuperSync FIFO is a trademark of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEATURES ••••• Choose among the following memory organizations: IDT72255LA — 8,192 x 18 IDT72265LA — 16,384 x 18 ••••• Pin-compatible with the IDT72275/72285 SuperSync FIFOs ••••• 10ns read/write cycle time (8ns access time) ••••• Fixed, low first word data latency time ••••• Auto power down minimizes standby power consumption ••••• Master Reset clears entire FIFO ••••• Partial Reset clears data, but retains programmable settings ••••• Retransmit operation with fixed, low first word data latency time ••••• Empty, Full and Half-Full flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets ••••• Program partial flags by either serial or parallel means ••••• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) ••••• Output enable puts data outputs into high impedance state ••••• Easily expandable in depth and width ••••• Independent Read and Write clocks (permit reading and writing simultaneously) ••••• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- pin Slim Thin Quad Flat Pack (STQFP) ••••• High-performance submicron CMOS technology ••••• Industrial temperature range (–40°C to +85°C) is available ••••• Green parts available, see ordering information DESCRIPTION The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: ••••• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. ••••• The period required by the retransmit operation is now fixed and short. ••••• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.) INPUT REGISTER OUTPUT REGISTER RAM ARRAY 8,192 x 18 16,384 x 18 FLAG LOGIC FF /IR PAF EF /OR PAE HF READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN WCLK D0 -D17 LD MRS REN RCLK OE Q0 -Q17 OFFSET REGISTER PRS FWFT/SI SEN RT 4670 drw01 FUNCTIONAL BLOCK DIAGRAM |
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