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January 19, 2006

IDT 79RC32435

P

PP

Pin Description Table

in Description Table

in Description Table

in Description Table

The following table lists the functions of the pins provided on the RC32435. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero

(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal

Type

Name/Description

Memory and Peripheral Bus

BDIRN

O

External Buffer Direction. Controls the direction of the external data bus buffer

for the memory and peripheral bus. If the RC32435 memory and peripheral bus

is connected to the A side of a transceiver, such as an IDT74FCT245, then this

pin may be directly connected to the direction control (e.g., BDIR) pin of the

transceiver.

BOEN

O

External Buffer Enable. This signal provides an output enable control for an

external buffer on the memory and peripheral data bus.

WEN

O

Write Enables. This signal is the memory and peripheral bus write enable sig-

nal.

CSN[3:0]

O

Chip Selects. These signals are used to select an external device on the mem-

ory and peripheral bus.

MADDR[21:0]

O

Address Bus. 22-bit memory and peripheral bus address bus.

MADDR[25:22] are available as GPIO alternate functions.

MDATA[7:0]

I/O

Data Bus. 8-bit memory and peripheral data bus. During a cold reset, these pins

function as inputs that are used to load the boot configuration vector.

OEN

O

Output Enable. This signal is asserted when data should be driven by an exter-

nal device on the memory and peripheral bus.

RWN

O

Read Write. This signal indicates whether the transaction on the memory and

peripheral bus is a read transaction or a write transaction. A high level indicates

a read from an external device. A low level indicates a write to an external

device.

WAITACKN

I

Wait or Transfer Acknowledge. When configured as wait, this signal is

asserted during a memory and peripheral bus transaction to extend the bus

cycle. When configured as a transfer acknowledge, this signal is asserted during

a transaction to signal the completion of the transaction.

DDR Bus

DDRADDR[13:0]

O

DDR Address Bus. 14-bit multiplexed DDR address bus. This bus is used to

transfer the addresses to the DDR devices.

DDRBA[1:0]

O

DDR Bank Address. These signals are used to transfer the bank address to the

DDRs.

DDRCASN

O

DDR Column Address Strobe. This signal is asserted during DDR transac-

tions.

DDRCKE

O

DDR Clock Enable. The DDR clock enable signal is asserted during normal

DDR operation. This signal is negated following a cold reset or during a power

down operation.

DDRCKN

O

DDR Negative DDR clock. This signal is the negative clock of the differential

DDR clock pair.

Table 1 Pin Description (Part 1 of 6)