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IDT72401L25SOB Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72401L25SOB Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 9 page 7 IDT72401/72403 CMOS PARALLEL FIFO 64 x 4, 64 x 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES Figure 7. tPT and tOPH Specification Figure 8. Master Reset Timing Figure 9. Output Enable Timing, IDT72403 Only NOTE: 1. High-Z transitions are referenced to the steady-state VOH –500mV and VOL +500mV levels on the output. tHZOE is tested with 5pF load capacitance instead of 30pF as shown in Figure 1. 2747 drw 14 IR SI Q0 SO OR MR D0 D1 D2 D3 IR SI Q0 Q1 Q2 Q3 SO OR MR SHIFT IN INPUT READY DATA IN MR OUTPUT READY SHIFT OUT DATA OUT Q1 Q2 Q3 D0 D1 D2 D3 NOTE: 1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. Figure 10. 128 x 4 Depth Expansion SI SO OR (1) tOPH tPT 2747 drw 11 DATA OUTPUT DATA VALID tSOR HZOE t 2747 drw 13 OE DATA OUT tOOE NOTE: 1. FIFO initially empty. MR IR OR tMRW 2747 drw 12 SI DATA OUTPUT tMRIRH tMRQ (1) (1) tMRORL tMRS NOTE: 1. Worst case, FIFO initially full. |
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