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IDT82V2044 Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT82V2044 Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 61 page  Pin Description 4 September 22, 2005 IDT82V2044 QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT 1 PIN DESCRIPTION Table-1 Pin Description Name Type Pin No. Description TQFP144 PBGA160 Transmit and Receive Line Interface TTIP0 TTIP1 TTIP2 TTIP3 TRING0 TRING1 TRING2 TRING3 Analog Output 45 52 57 64 46 51 58 63 N5 L5 L10 N10 P5 M5 M10 P10 TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~3 These pins are the differential line driver outputs. They will be in high-Z state if pin OE is low or the corre- sponding pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In host mode, each pin can be in high-Z by programming a ‘1’ to the corresponding bit in register OE(1). RTIP0 RTIP1 RTIP2 RTIP3 RRING0 RRING1 RRING2 RRING3 Analog Input 48 55 60 67 49 54 61 66 P7 M7 M8 P8 N7 L7 L8 N8 RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~3 These pins are the differential line receiver inputs. Transmit and Receive Digital Data Interface TD0/TDP0 TD1/TDP1 TD2/TDP2 TD3/TDP3 BPVI0/TDN0 BPVI1/TDN1 BPVI2/TDN2 BPVI3/TDN3 I 37 30 80 73 38 31 79 72 N2 L2 L13 N13 N3 L3 L12 N12 TDn: Transmit Data for Channel 0~3 When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code rules before being transmitted to the line. BPVIn: Bipolar Violation Insertion for Channel 0~3 Bipolar violation insertion is available in Single Rail mode 2 (see Table-2 on page 13 and Table-3 on page 14) with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing. TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~3 When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail mode is as the follow: Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding channel into Single Rail mode 1 (see Table-2 on page 13 and Table-3 on page 14). TDPn TDNn Output Pulse 0 0 Space 0 1 Negative Pulse 1 0 Positive Pulse 1 1 Space 1. Register name is indicated by bold capital letter. For example, OE indicates Output Enable Register. |
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