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IDT82V2054BB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT82V2054BB Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 56 page  Pin Description 6 September 22, 2005 IDT82V2054 QUAD E1 SHORT HAUL LINE INTERFACE UNIT RCLK0 RCLK1 RCLK2 RCLK3 O High-Z 39 32 78 71 P1 M1 M14 P14 RCLKn: Receive Clock for Channel 0~3 In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn. The received data are clocked out of the device on the rising edges of RCLKn if pin CLKE is high, or on falling edges of RCLKn if pin CLKE is low. In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with RDPn and RDNn. The clock is recovered from the signal on RCLKn. If Receiver n is powered down, the corresponding RCLKn is in high-Z. MCLK I 10 E1 MCLK: Master Clock This is an independent, free running reference clock. A clock of 2.048 MHz is supplied to this pin as the clock reference of the device for normal operation. In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse (Data Recovery mode). When MCLK is low, all the receivers are powered down, and the output pins RCLKn, RDPn and RDNn are switched to high-Z. In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn pin description for details). NOTE: Wait state generation via RDY/ACK is not available if MCLK is not provided. LOS0 LOS1 LOS2 LOS3 O 42 35 75 68 K4 K3 K12 K11 LOSn: Loss of Signal Output for Channel 0~3 A high level on this pin indicates the loss of signal when there is no transition over a specified period of time or no enough ones density in the received signal. The transition will return to low automatically when there is enough transitions over a specified period of time with a certain ones density in the received sig- nal. The LOS assertion and desertion criteria are described in 2.3.4 Loss of Signal (LOS) Detection. Hardware/Host Control Interface MODE2 I (Pulled to VDDIO/2) 11 E2 MODE2: Control Mode Select 2 The signal on this pin determines which control mode is selected to control the device: Hardware control pins include MODE[2:0], LP[3:0], CODE, CLKE, JAS and OE. Serial host Interface pins include CS, SCLK, SDI, SDO and INT. Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions below for details): MODE1 I 43 K2 MODE1: Control Mode Select 1 In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin is low, and operates with multiplexed address and data bus when this pin is high. In serial host mode or hardware mode, this pin should be grounded. Table-1 Pin Description (Continued) Name Type Pin No. Description TQFP144 PBGA160 MODE2 Control Interface Low Hardware Mode VDDIO/2 Serial Host Interface High Parallel Host Interface MODE[2:0] Host Interface 100 Non-multiplexed Motorola Interface 101 Non-multiplexed Intel Interface 110 Multiplexed Motorola Interface 111 Multiplexed Intel Interface |
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