PM6541 datasheet(6/49 Pages) PMC

Part #	PM6541

Description	E1XC EVALUATION DAUGHTERBOARD

Download	49 Pages

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Manufacturer	PMC [PMC-Sierra, Inc]

Direct Link	http://www.pmc-sierra.com

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6 / 49 page

PMC-Sierra, Inc.

PM6541 E1XC-EVBD

TELECOM STANDARD PRODUCT

PMC-930917

ISSUE 1

E1XC EVALUATION DAUGHTERBOARD

3

2.3

Decode Logic

Decode logic is provided on the daughterboard to give memory mapped access to

all of the registers within both E1XCs. Registers within the "east" E1XC are

accessible starting at address C000H. Registers within the "west" E1XC are

accessible starting at address C100H. Additional chip selects are provided for

addresses C200H-C2FFH and C300H-C3FFH for use on the prototype area.

2.4

DIP Switches

The DIP switch settings control the operational modes of the MT8940 DPLL device

that is used to generate the backplane clock. Access to the enable inputs for the

various clock outputs is also provided through these switches.

2.5

Clock DPLL

The MT8940 T1/CEPT Digital Trunk DPLL can provide a number of different clocks

with different methods of synchronization, depending upon its mode setting, which

can be used to drive the backplane interface of the E1XCs. The device can output

1.544 MHz, 2.048 MHz, and 4.096 MHz clocks in true or complement format. The

DPLL can be allowed to free-run or it can be synchronized to the receive frame

pulses of either E1XC. PLL control is accomplished with the DIP switches

connected to the inputs.

2.6

Oscillators

Up to four oscillators can be used on the E1XC EVBD daughterboard depending

upon the choice of configuration. The E1XC devices require a 49.152 MHz clock if

all of the device's features are to be utilized. Although two oscillator sockets are

provided, only a single oscillator is necessary if two E1XC devices are used. The

insertion of a jumper (J25) will join the two E1XC XCLK inputs together to allow the

single clock to drive both devices. If a T1XC device is used in place of one of the

E1XC devices then the jumper must be removed to isolate each clock line and a

37.056 MHz oscillator is used to drive the T1XC XCLK input.

The MT8940 DPLL device requires two oscillators to drive internal DPLLs, one at

12.355 MHz, and the other at 16.384 MHz. If the MT8940 is removed from the

daughterboard, then these oscillators can be replaced with ones directly compatible

with the backplane rate. Each oscillator output is directly accessible at header pins,

allowing connections to be made by connecting jumpers to the E1XC devices.

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