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IDT71P73204250BQ Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT71P73204250BQ Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 25 page 6.42 3 IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range Pin Definitions Symbol Pin Function Description DQ[X:0] Input/Output Synchronous Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data outputs are driven during a valid read operation. The outputs are aligned with the rising edge of both C and C during normal operation. When operating in a single clock mode (C and C tied high), the outputs are aligned with the rising edge of both K and K. When a Read operation is not initiated or LD is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read operation in progress completes. 2M x 8 -- DQ[7:0] 2M x 9 -- DQ[8:0] 1M x 18 -- DQ[17:0] 512K x 36 -- DQ[35:0] BW0, BW1 BW2, BW3 Input Synchronous Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device. 2M x 9 -- BW0 controls DQ[8:0] 1M x 18 -- BW0 controls DQ[8:0] and BW1 controls DQ[17:9] 512K x 36 -- BW0 controls DQ[8:0], BW1 controls DQ[17:9], BW2 controls DQ[26:18] and BW3 controls DQ[35:27] NW0, NW1 Input Synchronous Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the device. 2M x 8 -- NW0 controls D[3:0] and NW1 controls D[7:4]. SA Input Synchronous Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations. SA0, SA1 Input Synchronous Burst count address bits on x18 and x36 DDRll devices. These bits allow changing the burst order in read or write operations, or addressing to the individual word of a burst. See page 9 for all possible burst sequences. LD Input Synchronous Load Control Logic. Sampled on the rising edge of K. If LD is low, a four word burst read or write operation will initiate designated by the R/ W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations will not be initiated. R/ W Input Synchronous Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation should be a read or write. If R/ W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is high during the rising edge of K, the R/ W input will be ignored. C Input Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through DQ[X:0] when in single clock mode. CQ, CQ Output Clock Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data is three stated. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. 6431 tbl 02a |
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