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IDT77V1253 Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT77V1253 Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 44 page  3 TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS IDT77V1253 TABLE 1 — SIGNAL DESCRIPTIONS LINE SIDE SIGNALS SIGNAL NAME PIN NUMBER I/O SIGNAL DESCRIPTION RX0+,- 139, 138 In Port 0 positive and negative receive differential input pair. RX1+,- 133, 132 In Port 1 positive and negative receive differential input pair. RX2+,- 121, 120 In Port 2 positive and negative receive differential input pair. TX0+,- 4, 3 Out Port 0 positive and negative transmit differential output pair. TX1+,- 144, 143 Out Port 1 positive and negative transmit differential output pair. TX2+,- 110, 109 Out Port 2 positive and negative transmit differential output pair. UTILITY BUS SIGNALS SIGNAL NAME PIN NUMBER I/O SIGNAL DESCRIPTION AD[7:0] 101, 100, 99, 98, 96, 95, 94, 93 In/Out Utility bus address/data bus. The address input is sampled on the falling e dge of ALE. Data is output on this bus when a read is performed. Input data is sampled at the completion of a write operation. ALE 91 In Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling edge of ALE. ALE may be either high low when the AD bus is being used for data. CS 90 In Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain asserted at all times if desired. RD 89 In Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by deasserting WR and asserting RD and CS. WR 88 In Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled. MISCELLANEOUS SIGNALS SIGNAL NAME PIN NUMBER I/O SIGNAL DESCRIPTION DA 103 In Reserved signal. This input must be connected to logic low. DNC 12, 82, 105, 106 Out Do Not Connect. Do not connect these pins to anything external to the chip. They must remain open. INT 85 Out Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable via the interrupt Mask Registers. MA 114 In Reserved signal. This input must be connected to logic low. MB 115 In Reserved signal. This input must be connected to logic low. MM 6 In Reserved signal. This input must be connected to logic high. MODE[1:0] 7, 8 In Mod e Selects. They determine the configuration of the PHY/ATM interface. 00 = UTOPIA Level 2. 01 = UTOPIA Le vel 1. 10 = DPI. 11 is reserved. OSC 126 In TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mb ps; 64 MHz for 51.2 Mbps. RST 87 In Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed after power up prior to normal operation of the part. RXLED[2:0] 81, 80, 79 Out Receive LED drivers. Driven low for 223 RCLK or DPICLK cycles, beginning with RXSOC when that port receives a good (non-null and non-errored) cell. Drives 8 mA both high and low. One per port. 4781 tbl 01 |
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