CY7C1446AV33-167BGXC datasheet(6/31 Pages) CYPRESS

Part #	CY7C1446AV33-167BGXC

Description	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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6 / 31 page

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Document #: 38-05383 Rev. *E

Page 6 of 31

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1446AV33 (512K × 72)

Pin Configurations (continued)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

123456789

11

10

DQG

DQC

NC

DQPG

DQH

DQD

DQPD

DQPC

DQC

NC

DQH

DQPH

DQD

DQB

DQF

NC

DQPF

DQA

DQE

DQPA

DQPB

DQF

NC

DQA

DQPE

DQE

A

ADSP

ADV

A

NC

NC/72M

AA

A

AA

A

A1

A0

A

AA

A

NC/144M

NC/288M

NC/576M

GW

NC

BWSB

BWSF

BWSE

BWSA

BWSC

BWSG

BWSD

BWSH

TMS

TDI

TDO

TCK

NC

MODE

NC

VSS

NC

CLK

NC

VSS

VDD

VSS

NC/1G

VDD

NC

OE

CE3

CE1

CE2

ADSC

BW

VSS

ZZ

VSS

NC

VDDQ

VSS

NC

VSS

NC

VSS

VDDQ

NC

VDDQ

NC

VDDQ

NC

VDDQ

Pin Definitions

Name

I/O

Description

A0, A1, A

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3

[2]are sampled active.

A1: A0 are fed to the two-bit counter.

BWA, BWB,

BWC, BWD,

BWE, BWF,

BWG, BWH

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the

SRAM. Sampled on the rising edge of CLK.

GW

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,

a global write is conducted (ALL bytes are written, regardless of the values on BWX and

BWE).

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal

must be asserted LOW to conduct a byte write.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment

the burst counter when ADV is asserted LOW, during a burst operation.

CE1

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is

sampled only when a new external address is loaded.

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CY7C1446AV33-167BGXC Datasheet(PDF) 6 Page - Cypress Semiconductor

CY7C1446AV33-167BGXC Datasheet(HTML) 6 Page - Cypress Semiconductor

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