CY7C1461AV33
CY7C1463AV33
CY7C1465AV33
Document #: 38-05356 Rev. *F
Page 11 of 31
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE1 CE2 CE3
ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H Tri-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H Tri-State
Read Cycle (Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out
(Q)
Read Cycle (Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out
(Q)
NOP/Dummy Read
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H Tri-State
Dummy Read (Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H Tri-State
Write Cycle (Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H Tri-State
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H Tri-State
Ignore Clock Edge (Stall)
Current
X
X
X
L
X
X
X
X
H
L->H
–
Sleep Mode
None
XXX
H
X
XXXXX
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
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