CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *J
Page 9 of 32
Functional Overview
The CY7C1471V33, CY7C1473V33, and CY7C1475V33 are
synchronous flow through burst SRAMs designed specifically
to eliminate wait states during write-read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If (CEN)
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be
a read or write operation, depending on the status of the Write
Enable (WE). Byte Write Select (BWX) can be used to conduct
Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (reads, writes, and deselects) are pipelined.
ADV/LD must be driven LOW after the device is deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied
at clock rise:
•CEN is asserted LOW
•CE1, CE2, and CE3 are ALL asserted active
•WE is deasserted HIGH
•ADV/LD is asserted LOW.
The address presented to the address inputs is latched into
the Address Register and presented to the memory array and
control logic. The control logic determines that a read access
is in progress and allows the requested data to propagate to
the output buffers. The data is available within 6.5 ns
(133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW to
drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, output is be tri-stated immediately.
Burst Read Accesses
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have
an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without
reasserting the address inputs. ADV/LD must be driven LOW
to load a new address into the SRAM, as described in the
Single Read Access section. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an inter-
leaved burst sequence. Both burst counters use A0 and A1 in
the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (read or write) is maintained throughout the
burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) WE is asserted
LOW. The address presented to the address bus is loaded into
the Address Register. The Write signals are latched into the
Control Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX
(or a subset for Byte Write operations, see “Truth Table for
Read/Write” on page 12 for details) inputs is latched into the
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
TDO
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be left unconnected. This pin is not available on
TQFP packages.
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be left floating or connected to VDD through a pull up resistor. This
pin is not available on TQFP packages.
TMS
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
JTAG
-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
NC
-
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
Pin Definitions (continued)
Name
IO
Description
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