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IDT7M9514SE150M Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT7M9514SE150M Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 7 page 6 1999 Integrated Device Technology, Inc. © IDT IDT7M9510 / IDT7M9514 7M9510SR Version The "SR" version of the 7M9510 is intended for customers using the I-Cube RaptorTM Fast Ethernet Switch Design. In this configuration, the Boot ROM shipped with the 7M9510 contains the most recent version of the I-Cube "Mini- Boot Monitor" (MBM). For applications other than the I-Cube RaptorTM Reference Design and the I-Cube FPGA configuration PROM, the recom- mended board configuration is the 7M9510SE which ships with IDT/Sim and IDT FPGA configuration PROM. 7M9510SE Version (EVALUATION) The "SE" version of the 7M9510 is packaged to support software develop- mentandprototyping. CurrentlytheEvaluationpackagecontainsthefollowing material: - 1 7M9510S - 1 8MB (2M x 32) EDO DRAM SIMM - 1 512KB (512K x 8) IDT/Sim Boot ROM Alternately, the 7M9710 Development Kit may be ordered. This kit includes all of the 7M9510SE components listed above. In addition the 7M9710 includes the following items: - 1 set of 7M9510 board schematics - 1 copy of 7M9510 Datasheet - 2 10 pin Serial Port to DB9 Adapter Cables - 2 6 foot DB9 to DB9 null modem serial cables - 1 7M9502 PCI Backplane - 1 7M9710 Quickstart Guide 4 N P ) 1 ( # n i Pe m a N l a n g i Se m a N l a n g i S# n i P 11 # O /I R E S UC N2 33 # O /I R E S UC N4 55 # O /I R E S U6 # O /I R E S U6 77 # O /I R E S U8 # O /I R E S U8 99 # O /I R E S U0 1 # O /I R E S U0 1 1 11 1 # O /I R E S U2 1 # O /I R E S U2 1 3 13 1 # O /I R E S U4 1 # O /I R E S U4 1 5 1C N6 1 # O /I R E S U6 1 7 1C NC N8 1 8 1C NC N0 2 1 21 2 # O /I R E S U2 2 # O /I R E S U2 2 3 23 2 # O /I R E S U4 2 # O /I R E S U4 2 5 2C N6 2 # O /I R E S U6 2 7 27 2 # O /I R E S U8 2 # O /I R E S U8 2 9 29 2 # O /I R E S U0 3 # O /I R E S U0 3 1 3C NC N2 3 3 33 3 # O /I R E S U4 3 # O /I R E S U4 3 5 3C NC N6 3 7 3C NC N8 3 9 3C NC N0 4 1 4C NC N2 4 3 4C NC N4 4 5 4C NC N6 4 7 4C NC N8 4 9 4C NC N0 5 1 5C NC N2 5 3 5C NC N4 5 5 5C NC N6 5 7 57 5 # O /I R E S U8 5 # O /I R E S U8 5 9 59 5 # O /I R E S U0 6 # O /I R E S U0 6 1 61 6 # O /I R E S U2 6 # O /I R E S U2 6 3 63 6 # O /I R E S U4 6 # O /I R E S U4 6 NOTES: 1. All of the User I/O pins are mapped through the on board FPGA. 4095 tbl 06 |
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