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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 3 of 28
4M x 18 Array
Write
Reg
Write
Reg
Logic Block Diagram (CY7C1518V18)
CLK
A(21: 0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[17: 0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS[1: 0]
VREF
18
22
C
C
18
LD
Control
Burst
Logic
A0
A(21:1)
21
CQ
CQ
R/W
DOFF
Logic Block Diagram (CY7C1520V18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[35: 0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS[3:0]
VREF
36
21
C
C
36
LD
Control
Burst
Logic
A0
A(20:1)
20
2M x 36 Array
Write
Reg
Write
Reg
CQ
CQ
36
R/W
DOFF
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