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IDTRC5000-200G Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDTRC5000-200G Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 16 page  IDT RC5000 COMMERCIAL TEMPERATURE RANGE 2 DESCRIPTION The RC5000 serves many performance critical embedded applications, such as high-end internet- working systems, color printers, and graphics terminals. The RC5000 is optimized for high-performance appli- cations, with special emphasis on system bandwidth and floating point operations, through integration of high- performance computational units and a high-performance memory hierarchy. For this class of application, the result is a relatively low-cost CPU capable of approximately 330 Dhrystone MIPS. IDT’s objectives in offering the RC5000 include: • Offering a high performance upgrade path to existing embedded customers in the internetworking, office automation and visualization markets. • Providing a significant improvement in the floating- point performance currently available in a moderately priced MIPS CPU. • Providing improvements in the memory hierarchy of desktop systems by using large primary caches and integrating a secondary cache controller. • Enabling improvements in performance through the use of the MIPS-IV ISA. Instruction Issue Mechanism The RC5000 recognizes two general classes of instructions for multi-issue: • Floating-point ALU • All others These instruction classes are pre-decoded by the RC5000, as they are brought on-chip. The pre-decoded information is stored in the instruction cache. Assuming that there are no pending resource conflicts, the RC5000 can issue one instruction per class per pipeline clock cycle. Note that this broad separation of classes insures that there are no data dependencies to restrict multi-issue. However, long-latency resources in either the floating- point ALU (e.g. DIV or SQRT instructions) or instructions in the integer unit (such as multiply) can restrict the issue of instructions. Note that the R5000 does not perform out- of-order or speculative execution; instead, the pipeline slips until the required resource becomes available. There are no alignment restrictions on dual-issue instruction pairs. The RC5000 fetches two instructions from the cache per cycle. Thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, since the instruction cache only performs aligned fetches. Instruction Set Architecture The RC5000 implements the MIPS-IV 64-bit ISA, including CP1 and CP1X functional units (and their instruction set). Integer Pipeline The RC5000 is a limited dual-issue machine that utilizes a traditional 5-stage integer pipeline. This basic integer pipeline of the RC5000 is illustrated in Figure 1. The integer instruction execution speed is tabulated (in number of pipeline clocks) as follows: The RC5000’s short pipeline keeps the load and branch latencies very low. The caches contain special logic that allows any combination of loads and stores to execute in back-to-back cycles without requiring pipeline slips or stalls. (This presumes, of course, that the opera- tion does not miss in the cache.) Operation Latency Repeat Load 2 1 Store 2 1 MULT/MULTU 8 8 DMULT/DMULTU 12 12 DIV/DIVU 36 36 DDIV/DDIVU 68 68 Other Integer ALU 1 1 Branch 2 2 Jump 2 2 |
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