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CY7C1463AV33-100BZI Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1463AV33-100BZI
Description  36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1463AV33-100BZI Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C1461AV33
CY7C1463AV33
CY7C1465AV33
Document #: 38-05356 Rev. *E
Page 11 of 29
NOP/Dummy Read
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Dummy Read (Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
Write Cycle (Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Ignore Clock Edge (Stall)
Current
X
X
X
L
X
X
X
X
H
L->H
Sleep Mode
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Truth Table for Read/Write[2, 3]
Function (CY7C1461AV33)
WE
BWA
BWB
BWC
BWD
Read
H
XXXX
Write No bytes written
L
HHHH
Write Byte A – (DQA and DQPA)
L
L
HHH
Write Byte B – (DQB and DQPB)L
H
L
H
H
Write Byte C – (DQC and DQPC)L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
HHH
L
Write All Bytes
LLLL
L
Truth Table[2,3,4,5,6,7,8] (continued)
Operation
Address
Used
CE1 CE2 CE3 ZZ ADV/LD WE BWX OE
CEN
CLK
DQ
Truth Table for Read/Write[2, 3]
Function (CY7C1463AV33)
WE
BWb
BWa
Read
H
X
X
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)L
H
L
Write Byte b – (DQb and DQPb)L
L
H
Write Both Bytes
L
L
L
Truth Table for Read/Write[2,3, 9]
Function (CY7C1465AV33)
WE
BWx
Read
HX
Write – No Bytes Written
L
H
Write Byte X
− (DQ
x and DQPx)
LL
Write All Bytes
L
All BW = L
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active
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