CY7C67300
Document #: 38-08015 Rev. *H
Page 7 of 98
Figure 4 illustrates the interface for connecting an 8-bit ROM
or 8-bit RAM to the EZ-Host external memory interface. In 8-bit
mode, up to 512K bytes of external ROM or RAM are
supported.
General Purpose IO Interface (GPIO)
EZ-Host has up to 32 GPIO signals available. Several other
optional interfaces use GPIO pins as well and may reduce the
overall number of available GPIOs.
GPIO Description
All Inputs are sampled asynchronously with state changes
occurring at a rate of up to two 48 MHz clock cycles. GPIO pins
are latched directly into registers, a single flip-flop.
Unused Pin Descriptions
Ensure to tristate unused USB pins with the D+ line pulled high
through the internal pull up resistor and the D– line pulled low
through the internal pull down resistor.
Configure unused GPIO pins as outputs so they are driven low.
UART Interface
EZ-Host has a built in UART interface. The UART interface
supports data rates from 900 to 115.2K baud. It can be used
as a development port or for other interface requirements. The
UART interface is exposed through GPIO pins.
UART Features
• Supports baud rates of 900 to 115.2K
•8-N-1
UART Pins.
I2C EEPROM Interface
EZ-Host provides a master-only I2C interface for external
serial EEPROMs. The serial EEPROM can be used to store
application specific code and data. Use the I2C interface for
loading code out of EEPROM, it is not a general I2C interface.
The I2C EEPROM interface is a BIOS implementation and is
exposed through GPIO pins. Refer to the BIOS documentation
for additional details on this interface.
I2C EEPROM Features
• Supports EEPROMs up to 64 KB (512K bit)
• Auto-detection of EEPROM size
I2C EEPROM Pins
Serial Peripheral Interface
EZ-Host provides a SPI interface for added connectivity.
EZ-Host may be configured as either an SPI master or SPI
slave. The SPI interface can be exposed through GPIO pins
or the External Memory port.
SPI Features
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8-byte receive FIFO and 8-byte transmit FIFO
• Selectable master SPI clock rates from 250 kHz to 12 MHz
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz
• Maskable interrupts for block and byte transfer modes
• Individual bit transfer for non-byte aligned serial communi-
cation in PIO mode
• Programmable delay timing for the active/inactive master
SPI clock
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
Figure 4. Interfacing up to 512k × 8 for External Code/Data
Table 7.
UART Interface Pins
Pin Name
Pin Number
TX
42
RX
43
EZ-Host
CY7C67300
External Memory Array
Up to 512k x8
A[18:0]
nWR
nRD
nXMEMSEL
A[18:0]
WE
OE
CE
D[7:0]
D[7:0]
Up to 512k x 8 External Code/Data (Page Mode)
Table 8.
I2C EEPROM Interface Pins
Pin Name
Pin Number
GPIO Number
SMALL EEPROM
SCK
39
GPIO31
SDA
40
GPIO30
LARGE EEPROM
SCK
40
GPIO30
SDA
39
GPIO31
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