CDB5504 datasheet(4/24 Pages) CIRRUS | Low Power, 20-Bit A/D Converter

4 page

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;

VA- = -5V

± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter

Symbol

Min

Typ

Max

Units

Master Clock Frequency

Internal Oscillator

External Clock

XIN

fclk

30.0

32.768

53.0

330

kHz

Master Clock Duty Cycle

Rise Times:

Any Digital Input

(Note 9)

Any Digital Output

trise

1.0

µs

Fall Times:

Any Digital Input

(Note 9)

Any Digital Output

tfall

1.0

µs

Start-Up

Power-On Reset Period

(Note 10)

tres

-10

Oscillator Start-up Time

XTAL = 32.768 kHz (Note 11)

tosu

500

Wake-up Period

(Note 12)

twup

1800/fclk

-s

Calibration

CONV Pulse Width (CAL=1)

(Note 13)

tccw

100

CONV and CAL High to Start of Calibration

tscl

2/fclk+200

Start of Calibration to End of Calibration

tcal

3246/fclk

-s

Conversion

Set Up Time

A0 to CONV High

tsac

Hold Time

A0 after CONV High

thca

100

CONV Pulse Width

tcpw

100

CONV High to Start of Conversion

tscn

2/fclk+200

Set Up Time

BP/UP stable prior to DRDY falling

tbus

82/fclk

Hold Time

BP/UP stable after DRDY falls

tbuh

Start of Conversion to End of Conversion

(Note 14)

tcon

1624/fclk

-s

Notes:

9. Specified using 10% and 90% points on waveform of interest.

10. An internal power-on-reset is activated whenever power is applied to the device.

11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when

using an external clock source.

12. The wake-up period begins once the oscillator starts; or when using an external fclk, after the

power-on reset time elapses.

13. Calibration can also be initiated by pulsing CAL high while CONV=1.

14. Conversion time will be 1622/fclk if CONV remains high continuously.

CS5504

DS126F1

CS5504

DS126F2

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