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CY7C1527V18-167BZXI Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1527V18-167BZXI
Description  72-Mbit DDR-II SRAM 2-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1527V18-167BZXI Datasheet(HTML) 1 Page - Cypress Semiconductor

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72-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-05563 Rev. *D
Revised June 1, 2006
Features
• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1516V18 – 8M x 8
CY7C1527V18 – 8M x 9
CY7C1518V18 – 4M x 18
CY7C1520V18 – 2M x 36
Functional Description
The CY7C1516V18, CY7C1527V18, CY7C1518V18, and
CY7C1520V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock.Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1516V18 and two 9-bit words in the case of
CY7C1527V18 that burst sequentially into or out of the device.
The burst counter always starts with a “0” internally in the case
of CY7C1516V18 and CY7C1527V18. On CY7C1518V18 and
CY7C1520V18, the burst counter takes in the least significant
bit of the external address and bursts two 18-bit words in the
case of CY7C1518V18 and two 36-bit words in the case of
CY7C1520V18 sequentially into or out of the device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR SRAM in
the system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current (x36)
900
860
800
700
650
mA
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