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September 18, 2006
Document No. 001-05356 Rev. *B
8
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet
1. Pin Information
1.1.2
24-Pin Part Pinout
Table 1-2. 24-Pin Part Pinout (QFN**)
Pin
No.
Type
Name
Description
CY8C20334 24-Pin PSoC Device
Digital
Analog
1
IO
I
P2[5]
2
IO
I
P2[3]
3
IO
I
P2[1]
4
IOH
I
P1[7]
I2C SCL, SPI SS.
5
IOH
I
P1[5]
I2C SDA, SPI MISO.
6
IOH
I
P1[3]
SPI CLK.
7
IOH
I
P1[1]
CLK*, I2C SCL, SPI MOSI.
8
NC
No connection.
9
Power
Vss
Ground connection.
10
IOH
I
P1[0]
DATA*, I2C SDA.
11
IOH
I
P1[2]
12
IOH
I
P1[4]
Optional external clock input (EXTCLK).
13
IOH
I
P1[6]
14
Input
XRES
Active high external reset with internal
pull down.
15
IO
I
P2[0]
16
IO
I
P0[0]
17
IO
I
P0[2]
18
IO
I
P0[4]
19
IO
I
P0[6]
Analog bypass.
20
Power
Vdd
Supply voltage.
21
IO
I
P0[7]
22
IO
I
P0[5]
23
IO
I
P0[3]
Integrating input.
24
IO
I
P0[1]
CP
Power
Vss
Center pad must be connected to
ground.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
QFN
(Top View )
AI,P2[5]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[2],AI
P0[0],AI
P0[4],AI
AI,P2[3]
AI,P2[1]
P1[6],AI
XRES
P2[0],AI
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