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CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *K
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EP2–1024
double
buffered;
EP6–512
quad
buffered
(column 8).
3.12.5
Default Full-Speed Alternate Settings
3.12.6
Default High-Speed Alternate Settings
64
64
64
512
512
1024
1024
1024
1024
1024
1024
1024
512
512
512
512
512
512
512
512
512
512
EP2
EP2 EP2
EP6
EP6
EP8
EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
Figure 3-5. Endpoint Configuration
1024
1024
EP6
1024
512
512
EP8
512
512
EP6
512
512
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
512
512
EP2
512
512
512
512
EP2
512
512
1024
EP2
1024
1024
EP2
1024
1024
EP2
1024
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1
2
3
4
5
6
7
8
9
10
11
12
Table 3-6. Default Full-Speed Alternate Settings[4, 5]
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
0
64 bulk
64 int
64 int
ep1in
0
64 bulk
64 int
64 int
ep2
0
64 bulk out (2×)
64 int out (2×)
64 iso out (2×)
ep4
0
64 bulk out (2×)
64 bulk out (2×)
64 bulk out (2×)
ep6
0
64 bulk in (2×)
64 int in (2×)
64 iso in (2×)
ep8
0
64 bulk in (2×)
64 bulk in (2×)
64 bulk in (2×)
Notes:
4.
“0” means “not implemented.”
5.
“2×” means “double buffered.”
6.
Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Table 3-7. Default High-Speed Alternate Settings[4, 5]
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
0
512 bulk[6]
64 int
64 int
ep1in
0
512 bulk[6]
64 int
64 int
ep2
0
512 bulk out (2×)
512 int out (2×)
512 iso out (2×)
ep4
0
512 bulk out (2×)
512 bulk out (2×)
512 bulk out (2×)
ep6
0
512 bulk in (2×)
512 int in (2×)
512 iso in (2×)
ep8
0
512 bulk in (2×)
512 bulk in (2×)
512 bulk in (2×)
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