CY14B101K
PRELIMINARY
Document #: 001-06401 Rev. *E
Page 8 of 24
compared to the terminal value of 0. If the counter reaches this
value, it causes an internal flag and an optional interrupt
output. You can prevent the timeout interrupt by setting WDS
bit to 1 before the counter reaching 0. This causes the counter
to be reloaded with the watchdog timeout value and to be
restarted. As long as the user sets the WDS bit before the
counter reaching the terminal value, the interrupt and flag
never occurs.
Write new timeout values by setting the watchdog WRITE bit
to 0. When the WDW is 0 (from the previous operation), new
writes to the watchdog timeout value bits D5–D0 allow the
timeout value to be modified. When WDW is a 1, writes to bits
D5 – D0 will be ignored. The WDW function allows a user to
set the WDS bit without concern that the watchdog timer value
will be modified. A logical diagram of the watchdog timer is
shown in Figure 3. Note that setting the watchdog timeout
value to 0 would be otherwise meaningless and therefore
disables the watchdog function.
The output of the watchdog timer is a flag bit WDF that is set
if the watchdog is allowed to timeout. The flag is set upon a
watchdog timeout and cleared when the Flags/Control register
is READREAD by the user. The user can also enable an
optional interrupt source to drive the INT pin if the watchdog
timeout occurs.
Power Monitor
The CY14B101K provides a power management scheme with
power fail interrupt capability. It also controls the internal
switch to backup power for the clock and protects the memory
from low VCC access. The power monitor is based on an
internal band gap reference circuit that compares the VCC
voltage to various thresholds.
As described in the AutoStore section previously, when
VSWITCH is reached as VCC decays from power loss, a data
store operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor)
to operate the RTC oscillator.
When operating from the backup source no data may be read
or written and the clock functions are not available to the user.
The clock continues to operate in the background. Updated
clock data is available to the user after VCC has been restored
to the device and tHRECALL delay (see AutoStore/Power Up
RECALL on page 16) .
Interrupts
The CY14B101K provides three potential interrupt sources.
They include the watchdog timer, the power monitor, and the
clock/calendar alarm. Individually enable each and assign to
drive the INT pin. In addition, each has an associated flag bit
that the host processor can use to determine the cause of the
interrupt. Some of the sources have additional control bits that
determine functional behavior. In addition, the pin driver has
three bits that specify its behavior when an interrupt occurs.
The three interrupts each have a source and an enable. Both
the source and the enable must be active (true high) in order
to generate an interrupt output. Only one source is necessary
to drive the pin. The user can identify the source by reading
the Flags/Control register, which contains the flags associated
with each source. All flags are cleared to 0 when the register
is READ. The flags will be cleared only after a complete read
cycle (WE high); The power monitor has two programmable
settings that are explained in the power monitor section.
Once an interrupt source is active, the pin driver determines
the behavior of the output. It has two programmable settings
as shown in the following section. Pin driver control bits are
located in the Interrupts register.
According to the programming selections, the pin can be
driven in the backup mode for an alarm interrupt. In addition,
the pin can be an active LOW (open drain) or an active HIGH
(push pull) driver. If programmed for operation during backup
mode, it can only be active LOW. Lastly, the pin can provide a
one shot function so that the active condition is a pulse or a
level condition. In one shot mode, the pulse width is internally
fixed at approximately 200 ms. This mode is intended to reset
a host microcontroller. In level mode, the pin goes to its active
polarity until the Flags/Control register is read by the user. This
mode is intended to be used as an interrupt to a host
microcontroller. The Interrupt register is initialized to 00h. The
control bits are summarized as follows:
Watchdog Interrupt Enable – WIE. When set to 1, the
watchdog timer drives the INT pin as well as an internal flag
when a watchdog timeout occurs. When WIE is set to 0, the
watchdog timer affects only the internal flag.
Alarm Interrupt Enable – AIE. When set to 1, the alarm
match drives the INT pin as well as an internal flag. When set
to 0, the alarm match only affects to internal flag.
Power Fail Interrupt Enable – PFE. When set to 1, the power
fail monitor drives the pin as well as an internal flag. When set
to 0, the power fail monitor affects only the internal flag.
High/Low – H/L. When set to a 1, the INT pin is active high
and the driver mode is push-pull. The INT pin can drive high
only when VCC > VSWITCH. When set to a 0, the INT pin is
active LOW and the drive mode is open drain. Active LOW
(open drain) is operational even in battery backup mode.
Pulse/Level – P/L. When set to a 1 and an interrupt occurs,
the INT pin is driven for approximately 200 ms. When P/L is
set to a 0, the INT pin is driven high or low (determined by H/L)
until the Flags/Control register is READd.
When an enabled interrupt source activates the INT pin, an
external host can READ the Flags/Control register to
determine the cause. Remember that all flags will be cleared
Figure 3. Watchdog Timer Block Diagram
1 Hz
Oscillator
Clock
Divider
Counter
Zero
Compare
WDF
WDS
Load
Register
WDW
D
Q
Q
Watchdog
Register
write to
Watchdog
Register
32 Hz
32,768 KHz
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
