CY14B101K
PRELIMINARY
Document #: 001-06401 Rev. *E
Page 9 of 24
when the register is READ. If the INT pin is programmed for
level mode, then the condition clears and the INT pin returns
to its inactive state. If the pin is programmed for pulse mode,
then reading the flag also clears the flag and the pin. The pulse
will not complete its specified duration if the Flags/Control
register is READ. If the INT pin is used as a host reset, then
the Flags/Control register should not be READ during a reset.
During a power on reset with no battery, the interrupt register
is automatically loaded with the value 24h. This causes power
fail interrupt to be enabled with an active LOW pulse.
Flags Register – The Flags register has three flag bits: WDF,
AF, and PF. These flag bits are initialized to 00h. These flags
are set by the watchdog timeout, alarm match, or power fail
monitor respectively. The processor can either poll this register
or enable interrupts to be informed when a flag is set. The flags
are automatically reset once the register is READ.
RTC Recommended Component Configuration
Figure 4. Interrupt Block Diagram
Recommended Values
Y1 = 32.768 KHz
RF = 10 M
Ω
C1 = 0
C2 = 56 pF
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
PF - Power F ail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
Watchdog
Timer
Power
Monitor
Clock
Alarm
VINT
WDF
WIE
PF
PFE
AF
AIE
P/L
Pin
Driver
H/L
INT
VCC
VSS
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