CY14B101K
PRELIMINARY
Document #: 001-06401 Rev. *E
Page 4 of 24
Hardware RECALL (Power Up)
During power up, or after any low power condition
(VCC <VSWITCH), an internal RECALL request will be latched.
When VCC once again exceeds the sense voltage of VSWITCH,
a RECALL cycle will be automatically initiated and takes
tHRECALL to complete.
Software STORE
Using a software address sequence, transfer the data from the
SRAM to the nonvolatile memory. The CY14B101K software
STORE
cycle
is
initiated
by
executing
sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If there are
intervening READ OR WRITE accesses, the sequence will be
aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE-controlled
READs or OE-controlled READs. Once the sixth address in
the sequence has been entered, the STORE cycle
commences and the chip will be disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence.
It is not necessary that OE be low for the sequence to be valid.
After the tSTORE cycle time has been fulfilled, the SRAM will
again be activated for READ and WRITE operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner
similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE-controlled
READ operations must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the tRECALL cycle time
the SRAM will once again be ready for READ and WRITE
operations.The RECALL operation does not alter the data in
the nonvolatile elements.
Preventing AutoStore
Disable the AutoStore function by initiating an AutoStore
Disable sequence. A sequence of READ operations is
performed in a manner similar to the software STORE
initiation. To initiate the AutoStore Disable sequence, the
following sequence of CE-controlled READ operations must
be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following sequence of
CE-controlled READ operations must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled a manual
STORE operation (Hardware or Software) needs to be issued
to save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore
enabled.
Data Protection
The CY14B101K protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC < VSWITCH. If the CY14B101K is in a WRITE mode
(both CE and WE low) at power up, after a RECALL, or after
a STORE, the WRITE will be inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brownout conditions.
Noise Considerations
The CY14B101K is a high-speed memory and so must have
a high-frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high-speed CMOS ICs,
careful routing of power, ground, and signals reduces circuit
noise.
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