CY2071A
Document #: 38-07139 Rev. *D
Page 4 of 9
Electrical Characteristics, Industrial 5.0V: VDD = 5.0V ±10%, TA = –40°C to 85°C
[8]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VOH
HIGH-Level Output Voltage
IOH = –4.0 mA
2.4
V
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
0.4
V
VIH
HIGH-Level Input Voltage[9]
Except Crystal Pins
2.0
V
VIL
LOW-Level Output Voltage[9]
Except Crystal Pins
0.8
V
IIH
Input HIGH Current
VIN = VDD – 0.5V
10
µA
IIL
Input LOW Current
VIN = 0.5V
150
µA
IOZ
Output Leakage Current
Three State Outputs
250
µA
IDD
VDD Supply Current
[10]
VDD = VDD max. 5V operation, CL = 25 pF
40
75
mA
Electrical Characteristics, Industrial 3.3V VDD =3.3V ±10%, TA = –40°C to +85°C
[8]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VOH
HIGH-Level Output Voltage
IOH = –4.0 mA
2.4
V
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
0.4
V
VIH
HIGH-Level Input Voltage[9]
Except Crystal Pins
2.0
V
VIL
LOW-Level Output Voltage[9]
Except Crystal Pins
0.8
V
IIH
Input HIGH Current
VIN = VDD – 0.5V
10
µA
IIL
Input LOW Current
VIN = 0.5V
150
µA
IOZ
Output Leakage Current
Three State Outputs
250
µA
IDD
VDD Supply Current
[10]
VDD = VDD max. 3.3V operation, CL = 15 pF
24
50
mA
Notes:
11. Guaranteed by design, not 100% tested.
12. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF.
13. Reference Output duty cycle depends on XTALIN duty cycle.
14. Measured at 1.4V.
Switching Characteristics, Commercial 5.0V[11]
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range 5V
operation 25-pF load
CY2071A
7.692
[130 MHz]
2000
[500 kHz]
ns
CY2071AF
10
[100 MHz]
2000
[500 kHz]
ns
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
0.8
1
%
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz
≤ f
OUT ≤ 50 MHz)
350
500
ps
t1C
Clock Jitter[12]
Peak-to-peak period jitter (fOUT > 50 MHz)
250
350
ps
Output Duty Cycle
Duty cycle[13, 14] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
45%
50%
55%
Output Duty Cycle[12] Duty cycle[14] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
40%
50%
60%
t3
Rise Time[12]
Output clock rise time
1.5
2.5
ns
t4
Fall Time[12]
Output clock fall time
1.5
2.5
ns
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
0.5
ns
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