CY14B104L/CY14B104N
PRELIMINARY
Document #: 001-07102 Rev. *E
Page 10 of 21
AC Test Conditions
Input Pulse Levels ................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%) ....................... <5 ns
Input and Output Timing Reference Levels ....................1.5V
Notes
8. WE must be HIGH during SRAM read cycles.
9. Device is continuously selected with CE and OE both LOW.
10. Measured ±200 mV from steady state output voltage.
11. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
AC Switching Characteristics
Parameters
Description
15ns
25ns
45ns
Unit
Cypress
Parameters
Alt.
Parameters
Min
Max
Min
Max
Min.
Max.
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
15
25
45
ns
tRC
[8]
tRC
Read Cycle Time
15
25
45
ns
tAA
[9]
tAA
Address Access Time
15
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
12
20
ns
tOHA
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE
[10]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE
[10]
tHZ
Chip Disable to Output Inactive
7
10
15
ns
tLZOE
[10]
tOLZ
Output Enable to Output Active
0
0
0
ns
tHZOE
[10]
tOHZ
Output Disable to Output Inactive
7
10
15
ns
tPU
[7]
tPA
Chip Enable to Power Active
0
0
0
ns
tPD
[7]
tPS
Chip Disable to Power Standby
15
25
45
ns
tDBE
-
Byte Enale to Data Valid
10
12
22
ns
tLZBE
-
Byte Enable to Output Active
0
0
0
ns
tHZBE
-
Byte Disable to Output Inactive
7
10
22
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
15
25
45
ns
tPWE
tWP
Write Pulse Width
10
20
30
ns
tSCE
tCW
Chip Enable To End of Write
15
20
30
ns
tSD
tDW
Data Setup to End of Write
5
10
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
ns
tHZWE
[10,11]
tWZ
Write Enable to Output Disable
7
10
15
ns
tLZWE
[10]
tOW
Output Active after End of Write
3
3
3
ns
tBW
-
Byte Enable to End of Write
15
20
30
ns
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