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CY7C1515V18-300BZXC Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1515V18-300BZXC
Description  72-Mbit QDR?? II SRAM 4-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1515V18-300BZXC Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Document #: 38-05363 Rev. *D
Page 10 of 28
Write Cycle Descriptions CY7C1511V18 and CY7C1513V18) [3, 11]
BWS0/NWS0 BWS1/NWS1
KK
Comments
L
L
L–H
During the Data portion of a Write sequence
:
CY7C1511V18
− both nibbles (D
[7:0]) are written into the device,
CY7C1513V18
− both bytes (D
[17:0]) are written into the device.
L
L
L-H
During the Data portion of a Write sequence
:
CY7C1511V18
− both nibbles (D
[7:0]) are written into the device,
CY7C1513V18
− both bytes (D
[17:0]) are written into the device.
L
H
L–H
During the Data portion of a Write sequence
:
CY7C1511V18
− only the lower nibble (D
[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1513V18
− only the lower byte (D
[8:0]) is written into the device. D[17:9]
will remain unaltered.
L
H
L–H
During the Data portion of a Write sequence
:
CY7C1511V18
− only the lower nibble (D
[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1513V18
− only the lower byte (D
[8:0]) is written into the device. D[17:9]
will remain unaltered.
H
L
L–H
During the Data portion of a Write sequence
:
CY7C1511V18
− only the upper nibble (D
[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1513V18
− only the upper byte (D
[17:9]) is written into the device. D[8:0]
will remain unaltered.
H
L
L–H
During the Data portion of a Write sequence
:
CY7C1511V18
− only the upper nibble (D
[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1513V18
− only the upper byte (D
[17:9]) is written into the device. D[8:0]
will remain unaltered.
H
H
L–H
No data is written into the devices during this portion of a write operation.
H
H
L–H
No data is written into the devices during this portion of a write operation.
Note:
11. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table.NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
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