CY24271
Document Number: 001-00411 Rev. *B
Page 4 of 13
SMBus Protocol
The CY24271 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
DC specifications are modified to RAMBUS standard to support
1.8, 2.5, and 3.3 volt devices. Time-out detection and packet
error protocol SMBus features are not supported.
Input Clock Signal
The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).
When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in
DC Operating Conditions on page 7 and AC Operating Condi-
tions on page 8.
For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in Figure 2, provide a reference
voltage VTH at the REFCLKB pin. This determines the proper trip
point of REFCLK. For the range of VTH specified in DC Operating
Conditions on page 7, the outputs also meet the DC and AC
Operating Conditions tables.
SMBus Data Byte Definitions
Three data bytes are defined for the CY24271. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
The definition of Byte 2 is shown in Table 5, Table 6, and Table 7
on page 5. The upper five bits are the revision numbers of the
device and the lower three bits are the ID numbers assigned to
the vendor by Rambus.
Notes
4. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
5. Default mode of operation is at power up.
Table 4. Modes of Operation for CY24271
EN
/BYPASS RegTest RegA
RegB
RegC
RegD CLK0/CLK0B
CLK1/CLK1B
CLK2/CLK2B CLK3/CLK3B
L
X
X
X
X
X
X
High Z
High Z
High Z
High Z
H
X
1
X
X
X
X
Reserved for Vendor Test
H
L
0
X
X
X
X
REFCLK/
REFCLKB[4]
REFCLK/
REFCLKB
REFCLK/
REFCLKB
REFCLK/
REFCLKB
H
H
0
0
0
0
0
High Z
High Z
High Z
High Z
H
H
0
0
0
0
1
High Z
High Z
High Z
CLK/CLKB
H
H
0
0
0
1
0
High Z
High Z
CLK/CLKB
High Z
H
H
0
0
0
1
1
High Z
High Z
CLK/CLKB
CLK/CLKB
H
H
0
0
1
0
0
High Z
CLK/CLKB
High Z
High Z
H
H
0
0
1
0
1
High Z
CLK/CLKB
High Z
CLK/CLKB
H
H
0
0
1
1
0
High Z
CLK/CLKB
CLK/CLKB
High Z
H
H
0
0
1
1
1
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
H
H
0
1
0
0
0
CLK/CLKB
High Z
High Z
High Z
H
H
0
1
0
0
1
CLK/CLKB
High Z
High Z
CLK/CLKB
H
H
0
1
0
1
0
CLK/CLKB
High Z
CLK/CLKB
High Z
H
H
0
1
0
1
1
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
H
H
0
1
1
0
0
CLK/CLKB
CLK/CLKB
High Z
High Z
H
H
0
1
1
0
1
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
H
H
0
1
1
1
0
CLK/CLKB
CLK/CLKB
CLK/CLKB
High Z
HH
0[5]
1[5]
1[5]
1[5]
1[5]
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
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