CY24271
Document Number: 001-00411 Rev. *B
Page 10 of 13
Signal Waveforms
A physical signal that appears at the pins of a device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. Input and output voltage waveforms are defined as
shown in Figure 4. Both rise and fall times are defined between
the 20% and 80% points of the voltage swing, with the swing
defined as VH–VL.
Figure 5 shows the definition of the output crossing point. The
nominal crossing point between the complementary outputs is
defined as the 50% point of the DC voltage levels. There are two
crossing points defined: Vx+ at the rising edge of CLK and Vx–
at the falling edge of CLK. For some waveforms, both Vx+ and
Vx– are below Vx,nom (for example, if tCR is larger than tCF).
Jitter
This section defines the specifications that relate to timing uncer-
tainty (or jitter) of the input and output waveforms. Figure 6
shows the definition of cycle-to-cycle jitter with respect to the
falling edge of the CLK signal. Cycle-to-cycle jitter is the
difference between cycle times of adjacent cycles. Equal require-
ments apply rising edges of the CLK signal. Figure 7 shows the
definition
of
cycle-to-cycle
duty
cycle
error
(tDC,ERR).
Cycle-to-cycle duty cycle is defined as the difference between
tPW+ (high times) of adjacent differential clock cycles. Equal
requirements apply to tPW-, low times of the differential click
cycles.
Figure 4. Input and Output Waveforms
Figure 5. Crossing Point Voltage
Example External Resistor Values
and Termination Voltages for a 50
Ω Channel
Parameter
Value
Unit
R1
39.2
Ω
R2
66.5
Ω
R3
93.1
Ω
RT
49.9
Ω
RRC
200
Ω
VTS
2.5V
V
VT
1.2V
V
V
H
t
R
t
F
80 %
20 %
V
L
V
(t)
Vx.nom
CLK
CLKB
Vx+
Vx-
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