CY24488
Document #: 001-09608 Rev. *A
Page 3 of 15
The special crystal requirements are eliminated if the VCXO
feature is not needed. To disable the VCXO, the VIN pin must
be tied high, and the appropriate register values given in the
programming table must be programmed into the device.
The VCXO is completely analog, so there is infinite resolution
on the VCXO pull curve. The analog-to-digital converter steps
that are normally associated with a digital VCXO input are not
present in this device.
VCXO Profile
Figure 1 shows an example of what a VCXO profile looks like.
The analog voltage input is on the X-axis and the PPM range
is on the Y-axis. An increase in the VCXO input voltage results
in a corresponding increase in the output frequency. This has
the effect of moving the PPM from a negative to positive offset
Figure 1. VCXO Profile
Crystal Requirements
The crystal requirements for the CY24488 differ for the VCXO
and non-VCXO modes. In all cases, the device must be
programmed correctly for the specific crystal used, as
indicated in Table 2.
Crystals for Non-VCXO Mode
When not using the VCXO, the VIN pin should be tied high.
The CY24488 uses a standard AT-cut parallel resonant
crystal, which is available in a variety of packages. The key
crystal parameter is load capacitance (CL). The CY24488 has
programmable load capacitance, to match a range of crystal
CL values. The specific configurations are shown in Table 2.
Crystals with CL values outside this range are not recom-
mended.
Pullable Crystals for VCXO Mode
When the VCXO mode is used, the crystal requirements
increase considerably in order to ensure the pullable range
and glitch-free pulling. Table 2 lists the crystals that Cypress
has qualified for use with the CY24488, as well as the corre-
sponding programming configurations. Customers wishing to
use non-qualified crystals should first contact Cypress
technical support.
Output Configurations
CLKC, CLKD, and CLKE are the three primary synthesized
output clocks. For each one, the user can select from several
clock frequencies, as shown in the tables below. To do this,
find the desired frequency from the appropriate table, then use
the serial programming interface to write the specified
hexadecimal data into the specified memory addresses.
In some cases the data at a particular memory address
controls multiple functions, so only some of the bit values are
specified. Since a byte is the smallest unit of data that can be
written, it is necessary to construct the full data byte prior to
writing it. To do this, look in the other tables to find the correct
values for the other bits in that byte.
Any of the remaining output clocks (CLKF and CLKG) can be
configured to generate duplicate copies of any the three
primary clocks. Any of them can also drive a buffered version
of the reference crystal frequency.
Enabling and Disabling Output Clocks
All output clocks can be individually enabled or disabled. Only
CLKG is on at power on. All other clocks are off (driven low),
and their respective PLLs are off. When using the serial
programming interface to set an output to a desired frequency,
the PLL Lock Time (AC Parameters Table) applies.
When turning off an output, the output buffer and associated
PLL are turned off by different register addresses. Therefore it
is possible to turn off an output by programming just one byte,
but the PLL will continue to run and consume some power.
Therefore the PLL Lock Time does not apply when turning the
output back on.
The clock configuration tables also show a second off state
that also turns off the PLL, saving additional power. This
requires programming one or two additional bytes, and the
PLL Lock Time applies.
Output Drive Strength
Output drive strength is configurable, with 2 bits available to
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which is medium-high. This is the recommended setting for
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Table 10 shows which bits must be changed, and how to
integrate these bits with other control bits to create valid bytes
for shifting in.
The user may program any output to a lower drive strength if
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the highest. Note that the lowest setting is very weak and is
not suitable for most applications.
Output Supply Voltage
The clock outputs may be operated at either 3.3V or 2.5V.
CLKC has its own power pin (VDD1), while all other clocks are
powered by VDD2. VDD1 and VDD2 may be operated at
different voltages if desired. AVDD must always be 3.3V.
The CY24488 also has internal register settings that should be
configured for the actual output supply voltage. The default
settings are optimized for VDD1 = VDD2 = 3.3V. Table 10 and
Table 3 show the values that need to be programmed for 2.5V
supply voltage.
-200
-150
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
3
3.5
VCXO input [V]
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