4 / 7 page
CY25701JXC/FJXC
Document #: 38-07684 Rev. *E
Page 4 of 7
Application Circuit
Switching Waveforms
0.1 µF
VDD
1
2
3
4
OE
VSS
SSCLK
VDD
Power
CY25701
Figure 1. Application Circuit Diagram
Duty Cycle Timing (DC = t1A/t1B)
t1A
t1B
SSCLK
Figure 2. Duty Cycle Waveform
Output Rise/Fall Time
SSCLK
Tr
VDD
0V
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 3. Output Rise/Fall Time Waveform
Output Enable/Disable Timing
SSCLK
VDD
TOE1
VIL
VIH
OUTPUT
ENABLE
0V
(Asynchronous)
High Impedance
TOE2
Figure 4. Output Enable/Disable Timing Waveforms
[+] Feedback
[+] Feedback