PRELIMINARY
CY25402
CY25422
Document #: 001-12565 Rev. *A
Page 2 of 8
General Description
The CY25402 and CY25422 are two PLL programmable
Spread Spectrum Clock Generators used to reduce EMI found
in high-speed digital electronic systems. Both PLLs have
Spread Spectrum capability. The spread spectrum feature are
turned on or off using the control pin SSON.
The advantage of having two PLLs is that a single device can
generate up to two independent frequencies from a single
crystal or reference input frequency. Generally, a design
requires up to two oscillators to achieve the same result with
a single CY25402 or CY25422.
The device uses Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy significantly reduces the cost of complying with
regulatory
agency
(EMC)
requirements
and
improves
time-to-market without degrading the system performance.
The CY25402 and CY25422 use a factory/field-programmable
configuration memory array to provide customization for
output frequencies, frequency select options, spread charac-
teristics like spread percentage and modulation frequency,
output drive strength and crystal load capacitance. A
customized device are configured using CyberclocksTM
software or by contacting the factory.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range
for center spread is from ±0.125% to ±2.50%. The range for
down spread is from –0.25% to –5.0%. Contact the factory for
smaller or larger spread percentage amounts, if required.
The input to the CY25402 and CY25422 is either a crystal or
a clock signal. The input frequency range for crystals is 8 MHz
to 48 MHz, and for clock signals is 8 MHz to 166 MHz.
The CY25402 and CY25422 have up to three clock outputs
and each output has three possible input sources.There are
two frequency select lines FS(1:0) that provide an option to
select four different sets of frequencies among the two PLLs.
Each output has programmable output divider options. Output
1 has eight possible divider values and outputs 2–3 have four
possible divider values for maximum flexibility. The 2 bit or 3
bit output dividers are programmable providing a wide output
frequency range.
The outputs are glitch-free when frequency is switched using
output dividers. The outputs have a predictable phase
relationship if the clock source is the same PLL and divider
values are 2, 3, 4, or 6.
The CY25402 and CY25422 are available in an 8-pin SOIC
package with commercial and industrial operating temperature
ranges.
Pin Configuration
8 LD SOIC
1
2
3
4
8
7
6
5
XOUT
GND
CLK3/SSON
PD#/OE/FS1
XIN
VDD
CLK1
CLK2/FS0
Pin Description - Memory Programmable 2-PLL device with 2 Spread Spectrum PLLs
Pin Number
Name
I/O
Description
1
XIN
Input
Crystal or Clock Input
2
VDD
Power
Power Supply
3
CLK1
Output
Programmable Clock Output
4
CLK2/FS0
Output/input
Programmable Clock Output or FS0
5
PD#/OE/FS1
Input
Power Down, Output Enable or FS1
6
CLK3/SSON
Output/Input
Programmable Clock Output or SSON
7
GND
Power
Power Supply Ground
8
XOUT
Output
Crystal Output
Table 1. Supply Voltage Options
Device
VDD Supply Voltage
CY25402
CY25422
2.5V, 3.0V or 3.3V
1.8V
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