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CY22395
CY22394
Document #: 38-07186 Rev. *C
Page 3 of 17
CY22393
Logic Block Diagram — CY22395
XTALIN
XTALOUT
S2/SUSPEND
SDAT
SCLK
SHUTDOWN/OE
CONFIGURATION
FLASH
OSC.
PLL1
LCLKE
11-Bit P
8-Bit Q
PLL2
11-Bit P
8-Bit Q
PLL3
11-Bit P
8-Bit Q
4x4
Switch
Crosspoint
Divider
7-Bit
Divider
7-Bit
Divider
7-Bit
Divider
7-Bit
Divider
/2, /3, or /4
LCLKA
LCLKB
CLKC
LCLKD
LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD
Pin Configurations
1
2
3
4
5
6
7
8
9
10
CLKC
VDD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
SHUTDOWN/OE
S2/SUSPEND
AVDD
SCLK (S1)
SDAT (S0)
GND
CLKA
CLKB
16-pin TSSOP
11
12
13
14
15
16
CY22393
1
2
3
4
5
6
7
8
9
10
CLKC
VDD
AGND
XTALIN
XTALOUT
XBUF
P–CLK
P+ CLK
SHUTDOWN/OE
S2/SUSPEND
AVDD
SCLK (S1)
SDAT (S0)
GND
CLKA
CLKB
16-pin TSSOP
11
12
13
14
15
16
CY22394
1
2
3
4
5
6
7
8
9
10
CLKC
VDD
AGND
XTALIN
XTALOUT
LCLKD
LCLKE
SHUTDOWN/OE
S2/SUSPEND
AVDD
SCLK (S1)
SDAT (S0)
GND/LGND
LCLKA
LCLKB
16-pin TSSOP
11
12
13
14
15
16
CY22395
LVDD
Pin Definitions
Name
PinNumber
CY22393
PinNumber
CY22394
PinNumber
CY22395
Description
CLKC
1
1
1
Configurable clock output C
VDD
2
2
2
Power supply
AGND
3
3
3
Analog Ground
XTALIN
4
4
4
Reference crystal input or external reference clock input
XTALOUT
5
5
5
Reference crystal feedback
XBUF
6
6
N/A
Buffered reference clock output
LVDD
N/A
N/A
6
Low voltage clock output power supply
CLKD or LCLKD
7
N/A
7
Configurable clock output D; LCLKD referenced to LVDD
P– CLK
N/A
7
N/A
LV PECL output[1]
CLKE or LCLKE
8
N/A
8
Configurable clock output E; LCLKE referenced to LVDD
P+ CLK
N/A
8
N/A
LV PECL output[1]
Note
1. LVPECL outputs require an external termination network.
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