4 / 8 page
PRELIMINARY
CY25402
CY25422
Document #: 001-12565 Rev. *A
Page 4 of 8
AC Electrical Specifications
Parameter
Description
Conditions
Min.
Typ. Max. Unit
FIN (crystal)
Crystal Frequency
8
–
48
MHz
FIN (clock)
Input Clock Frequency (XIN)
8
–
166
MHz
FOUT
Output Clock Frequency
3
–
166
MHz
DC
Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in Figure 2; t1/t2,
50% of VDD
45
50
55
%
DC
Ref Out Duty Cycle
Ref In Min 45%, Max 55%
40
60
%
ER
CLK1-3 Rising Edge Rate
VDD = All, 20% to 80% VDD
0.8
–
–
V/ns
EF
CLK1-3 Falling Edge Rate
VDD = All, 20% to 80% VDD
0.8
–
–
V/ns
TCCJ1
Cycle-to-cycle Jitter
Configuration dependent. See Table 2
–-
–
ps
TLTJ
Long Term Jitter
Configuration dependent. See Table 2
–-
–
ns
T10
PLL Lock Time
–
–
3
ms
Table 2. Configuration Example for Jitter
Reference
Description
Max Jitter (ps) on
Output 1(48MHz)
Max Jitter (ps) on Output 2
(27 MHz)
Max Jitter (ps) on
Output 3 (166 MHz)
27MHz
TCCJ1
155
255
170
27MHz
TLTJ
770
580
630
48 MHz
TCCJ1
135
225
100
48 MHz
TLTJ
535
575
520
Recommended Crystal Specification for SMD Package
Parameter
Description
Range 1 Range 2 Range 3
Unit
Fmin
Minimum Frequency
8
14
28
MHz
Fmax
Maximum Frequency
14
28
48
MHz
R1(max)
Maximum Motional Resistance (ESR)
135
50
30
Ω
C0(max)
Maximum Shunt Capacitance
4
4
2
pF
CL(max)
Maximum Parallel Load Capacitance
18
14
12
pF
DL(max)
Maximum Crystal Drive Level
300
300
300
μW
Recommended Crystal Specification for Thru-Hole Package
Parameter
Description
Range 1 Range 2 Range 3
Unit
Fmin
Minimum Frequency
8
14
24
MHz
Fmax
Maximum Frequency
14
24
32
MHz
R1(max)
Maximum Motional Resistance (ESR)
90
50
30
Ω
C0(max)
Maximum Shunt Capacitance
7
7
7
pF
CL(max)
Maximum Parallel Load Capacitance
18
12
12
pF
DL(max)
Maximum Crystal Drive Level
1000
1000
1000
μW
[+] Feedback
[+] Feedback