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CY22395FXIT Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY22395FXIT
Description  Three-PLL Serial-Programmable Flash-Programmable Clock Generator
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY22395FXIT Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY22395
CY22394
Document #: 38-07186 Rev. *C
Page 11 of 17
CY22393
Serial Programming Interface Timing
Figure 4. Start and Stop Frame
Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data)
Absolute Maximum Conditions
Supply Voltage ............................................... –0.5V to +7.0V
DC Input Voltage ............................ –0.5V to + (AVDD + 0.5V)
Storage Temperature .................................. –65°C to +125°C
Junction Temperature .................................................. 125°C
Data Retention @ Tj=125×C................................. > 10 years
Maximum Programming Cycles ....................................... 100
Package Power Dissipation ......................................350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2000V
Latch up (per JEDEC 17) .................................... > ±200 mA
Stresses exceeding Absolute Maximum Conditions may
cause permanent damage to the device. These conditions are
stress ratings only. Functional operation of the device at these
or any other conditions beyond those indicated in the
operation sections of this data sheet is not implied. Extended
exposure to Absolute Maximum Conditions may affect
reliability.
Serial Programming Interface Timing Specifications
Parameter
Description
Min
Max
Unit
fSCLK
Frequency of SCLK
400
kHz
Start mode time from SDA LOW to SCL LOW
0.6
μs
CLKLOW
SCLK LOW period
1.3
μs
CLKHIGH
SCLK HIGH period
0.6
μs
tSU
Data transition to SCLK HIGH
100
ns
tDH
Data hold (SCLK LOW to data transition)
0
ns
Rise time of SCLK and SDAT
300
ns
Fall time of SCLK and SDAT
300
ns
Stop mode time from SCLK HIGH to SDAT HIGH
0.6
μs
Stop mode to Start mode
1.3
μs
SDAT
SCLK
START
Transition
to next Bit
STOP
SDAT
SCLK
DA6
DA5 DA0
R/W
ACK
RA7
RA6 RA1
RA0
ACK
STOP
START
ACK
D7
D6
D1
D0
++
+
+
+
+
[+] Feedback
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