CY22395
CY22394
Document #: 38-07186 Rev. *C
Page 7 of 17
CY22393
PLL*_En
This bit enables the PLL when HIGH. If PLL2 or PLL3 are not
enabled, then any output selecting the disabled PLL must
have a divider setting of zero (off). Since the PLL1_En bit is
dynamic, internal logic automatically turns off dependent
outputs when PLL1_En goes LOW.
DivSel
This bit controls which register is used for the CLKA and CLKB
dividers.
OscCap[5:0]
This controls the internal capacitive load of the oscillator. The
approximate effective crystal load capacitance is:
Set to zero for external reference clock.
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These
should always be set according to Table 5. The parameters
are the Crystal Frequency, Internal Crystal Parasitic Resis-
tance (available from the manufacturer), and the OscCap
setting during crystal start up, which occurs when power is
applied, or after shutdown is released. If in doubt, use the next
higher setting.
For external reference, the use Table 6.
Reserved
These bits must be programmed LOW for proper operation of
the device.
Serial Programming Bitmaps — Summary Tables
C
LOAD
6pF
OscCap
0.375pF
×
()
+
=
Table 5.
OscCap
00H–20H
20H–30H
30H–40H
Crystal Freq\ R
30
Ω
60
Ω
30
Ω
60
Ω
30
Ω
60
Ω
8–15 MHz
00
01
01
10
01
10
15–20 MHz
01
10
01
10
10
10
20–25 MHz
01
10
10
10
10
11
25–30 MHz
10
10
10
11
11
NA
Table 6.
External Freq (MHz)
1–25
25–50
50–90
90–166
OscDrv[1:0]
00
01
10
11
Addr
DivSel
b7
b6
b5
b4
b3
b2
b1
b0
08H
0
ClkA_FS[0]
ClkA_Div[6:0]
09H
1
ClkA_FS[0]
ClkA_Div[6:0]
0AH
0
ClkB_FS[0]
ClkB_Div[6:0]
0BH
1
ClkB_FS[0]
ClkB_Div[6:0]
0CH
–
ClkC_FS[0]
ClkC_Div[6:0]
0DH
–
ClkD_FS[0]
ClkD_Div[6:0]
0EH
–
ClkD_FS[2:1]
ClkC_FS[2:1]
ClkB_FS[2:1]
ClkA_FS[2:1]
0FH
–
Clk{C,X}_ACAdj[1:0]
Clk{A,B,D,E}_ACAdj[1:0]
PdnEn
Xbuf_OE
ClkE_Div[1:0]
10H
–
ClkX_DCAdj[1]
Clk{D,E}_DCAdj[1]
ClkC_DCAdj[1]
Clk{A,B}_DCAdj[1]
11H
–
PLL2_Q[7:0]
12H
–
PLL2_P[7:0]
13H
–
Reserved
PLL2_En
PLL2_LF[2:0]
PLL2_PO
PLL2_P[9:8]
14H
–
PLL3_Q[7:0]
15H
–
PLL3_P[7:0]
16H
–
Reserved
PLL3_En
PLL3_LF[2:0]
PLL3_PO
PLL3_P[9:8]
17H
–
Osc_Cap[5:0]
Osc_Drv[1:0]
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
