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CY62127DV30
Document #: 38-05229 Rev. *H
Page 6 of 11
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[16,17]
Read Cycle No. 2 (OE Controlled)[16,17,18]
Write Cycle No. 1 (WE Controlled)[14, 15, 19, 20, 21]
Notes:
16. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
17. WE is HIGH for Read cycle.
18. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
19. Data I/O is high-impedance if OE = VIH.
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
21. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
tBW
DON'T CARE
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